PCB Impedance Control: Complete Guide to Calculation, Stackup Design & Differential Pair Routing

PCB Impedance Control: Complete Guide to Calculation, Stackup Design & Differential Pair Routing

Without proper impedance control, high-speed PCB designs will suffer from severe signal reflection and distortion, leading to functional failure. Common high-speed signals including PCI bus, PCI-E, USB, Ethernet, DDR memory and LVDS all require strict impedance control. Impedance control is achieved through collaborative optimization of PCB design and manufacturing processes, combining EDA software simulation with factory process parameters to meet signal integrity requirements.

1. Core Transmission Line Structures for Impedance Control

Characteristic impedance of PCB traces is determined by trace geometry and surrounding dielectric materials. The two most common transmission line structures have different impedance characteristics and control accuracy:

Microstrip Line

A microstrip line consists of a surface copper trace on one side of a dielectric layer, with a full ground plane on the other side of the dielectric. When dielectric constant, trace width and distance to the ground plane are all controlled, characteristic impedance can be held within ±5% tolerance, making it the standard structure for outer-layer high-speed signals.

Stripline

A stripline is an inner-layer copper trace embedded between two conductive ground planes, surrounded by dielectric material on all sides. Impedance is determined by trace width, copper thickness, dielectric constant and distance between the two ground planes, with typical control accuracy of ±10%. It is used for inner-layer high-speed signal routing.

2. Multilayer PCB Stackup Structure & Material Parameters

Accurate impedance control starts with a clear understanding of multilayer PCB stackup structure and material parameters. Multilayer boards are fabricated by laminating core boards and prepreg (bonding sheets) together.

Core Board & Prepreg

Core board: A rigid, double-sided copper-clad laminate with fixed thickness, serving as the base structural material of multilayer boards.

Prepreg (bonding sheet): The adhesive material used to bond core boards together. It has a nominal initial thickness, which shrinks slightly during the hot-press lamination process.

Standard multilayer boards use prepreg for the two outermost dielectric layers, with standalone copper foil as the outer-layer copper.

Copper Foil Thickness

Standard inner and outer copper foil nominal thicknesses include 0.5OZ, 1OZ and 2OZ (1OZ ≈ 35μm / 1.4mil).

Outer copper foil gains approximately 1OZ of additional thickness after surface treatment processes such as plating.

Inner copper (copper on both sides of the core board) has final thickness very close to the nominal value, with only a few micrometers of reduction from etching.

Solder Mask

The outermost protective layer of PCBs, commonly called "green ink" (also available in yellow, black and other colors). Solder mask thickness is difficult to control precisely: it is thicker on copper-free areas than on copper traces, though copper traces still protrude slightly from the surface due to their base thickness.

Standard Material Parameters (Reference for FR4 Boards)

Surface Copper Foil

Available nominal base thicknesses: 12μm, 18μm, 35μm. Final processed thickness is approximately 44μm, 50μm and 67μm respectively.

Core Board

Standard general-purpose FR4 core such as S1141A double-sided copper clad, with multiple thickness specifications available from manufacturers.

Prepreg

Nominal original thickness by model:

7628 prepreg: 0.185mm

2116 prepreg: 0.105mm

1080 prepreg: 0.075mm

3313 prepreg: 0.095mm

Actual thickness after lamination is typically 10–15μm less than the nominal value. A single bonding layer can use 1 to 3 sheets of prepreg, with at least one sheet required (some manufacturers require a minimum of two sheets). For thicker dielectric requirements, copper can be etched off both sides of a core board and prepreg added to both sides to form a thicker bonding layer.

Solder Mask Thickness

Solder mask thickness on copper traces (C2): ≈ 8–10μm

Solder mask thickness on copper-free surface: varies with base copper thickness. For 45μm surface copper, C1 ≈ 13–15μm; for 70μm surface copper, C1 ≈ 17–18μm

Trace Cross-Section Shape

Etched PCB traces do not have a perfect rectangular cross-section, but form a trapezoidal shape. For example, on the TOP layer with 1OZ copper thickness, the top edge of the trace is approximately 1mil shorter than the bottom edge: a 5mil nominal line width results in a ~4mil top edge and ~5mil bottom edge. The difference increases with higher copper thickness.

Dielectric Constant

The dielectric constant of FR4 material ranges from 4.2 to 4.7, and decreases as signal frequency increases. Prepreg dielectric constant also varies with material thickness and resin content.

Dielectric Loss Factor

Dielectric loss (tan δ) refers to energy consumed by dielectric material under alternating electric fields. Standard S1141A FR4 has a typical dielectric loss factor of 0.015.

Minimum Manufacturable Trace Width & Spacing

4mil / 4mil for standard mass production processes.

3. Impedance Calculation Tools & Methods

After confirming stackup structure and material parameters, characteristic impedance can be calculated via professional EDA tools.

Common Calculation Tools

Cadence Allegro: Built-in impedance calculation function integrated with layout design.

Polar SI9000: Industry-standard dedicated impedance calculation tool, adopted by most PCB manufacturers for production impedance verification.

For inner-layer single-ended and differential impedance, calculation results from Polar SI9000 and Allegro are very close, with minor differences caused by process details such as trace cross-section shape.

Solder Mask Consideration for Surface Layer Impedance

For outer-layer signal impedance calculation, always select the Coated Microstrip model instead of the Surface Microstrip model. The Coated model accounts for the effect of solder mask on impedance, delivering more accurate results.

If the Surface model is used, apply empirical correction values per board manufacturer recommendations to compensate for solder mask effect: subtract 8Ω from calculated differential impedance, and subtract 2Ω from calculated single-ended impedance.

4. Differential Pair Routing Requirements for Impedance Control

Select Appropriate Routing Structure

Differential pairs can be routed as outer-layer microstrip differential or inner-layer stripline differential. Calculate target impedance using dedicated tools such as Polar SI9000 with reasonable parameter settings before layout.

Strict Parallel & Equal Spacing Rule

Differential pair traces must maintain consistent line width and fixed spacing along the entire routing length to keep differential impedance stable. Two parallel configurations are available: side-by-side routing on the same layer, and vertically stacked routing across two layers.

Prioritize Same-Layer Differential Routing

Same-layer side-by-side differential pairs are always preferred over interlayer stacked differential pairs. PCB manufacturing alignment accuracy between layers is much lower than same-layer etching accuracy, and lamination dielectric thickness variation causes larger differential impedance drift for interlayer differential pairs. Same-layer routing delivers far more consistent differential impedance control.

Conclusion

Precise impedance control is the foundation of high-speed PCB signal integrity. Accurate stackup design, confirmed factory material parameters, professional impedance calculation tools and standardized routing rules work together to achieve reliable impedance matching. Collaborating with PCB manufacturers early in the design phase to confirm process parameters ensures impedance targets are met in mass production.

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