Multilayer PCB Hole Copper Thickness Production | Causes & Solutions for No Copper in Plated Through-Holes

Multilayer PCB Hole Copper Thickness Production | Causes & Solutions for No Copper in Plated Through-Holes

Plated through-hole (PTH) copper is the backbone of multilayer PCB interconnection. For double-sided and multilayer circuit boards, every via and through-hole must be plated with copper inside the hole wall to create a reliable electrical connection between layers — a process known as through-hole plating or PTH (plated through-hole).

However, during manufacturing inspection, PCB fabricators occasionally discover holes with no copper or insufficient copper thickness after the electroless copper (sink copper) and electroplating processes. These defects — commonly called "hole no copper," "skip plating," or "voids in PTH" — can cause open circuits, signal integrity failures, and long-term reliability issues.

This guide explains the production process of hole copper in multilayer PCBs, analyzes the seven major root causes of copper-free holes, and provides corresponding improvement solutions.

1. The Hole Copper Plating Process in Multilayer PCBs

Before analyzing defects, it is important to understand the standard PTH process flow:

Drilling: Mechanical or laser drilling creates through-holes, blind vias, or buried vias in the multilayer stackup.

Desmear / Etchback: Removes epoxy smear (drilling residue) from the hole wall and slightly etches the glass fiber and resin to create a rough, bondable surface. This step is critical for adhesion.

Electroless Copper (Sink Copper): A chemical (non-electrical) process that deposits a thin layer of copper (typically 0.5–1.5μm) onto the drilled hole wall, making the non-conductive epoxy/glass surface conductive.

Panel Plating: Electroplating thickens the copper on the entire board surface and inside the holes to the required finished copper thickness (typically 20–25μm or more, per IPC-6012 Class 2/3 requirements).

Pattern Transfer: Dry film lamination, exposure, and development define the circuit pattern.

Pattern Plating: Additional copper and tin (or nickel/gold) electroplating on exposed areas.

Etching: Removes unwanted copper, with tin or other resist protecting the circuit.

Hole copper defects can originate at any stage from drilling through final etching.

2. Seven Major Causes of Copper-Free Holes

2.1 Drilling Dust Plugging Holes or Rough Hole Walls

Drilling generates epoxy dust and glass fiber debris. If not properly removed, this debris can plug small-diameter holes (especially ≤0.3mm) or adhere to the hole wall, preventing the electroless copper from depositing uniformly. Rough hole walls — caused by dull drill bits, improper feed/speed, or insufficient drill withdrawal — can also trap debris and create weak copper adhesion.

Improvement: For holes prone to dust accumulation (especially those below 0.3mm), add a high-pressure water washing step and a degreasing/cleaning process after drilling. Ensure drill bits are sharp and replaced at the correct interval, and optimize drilling parameters (spindle speed, feed rate, and retract speed) for the substrate material.

2.2 Air Bubbles Trapped in the Plating Solution

During electroless copper plating (sink copper), air bubbles can become trapped inside the holes — particularly in high-aspect-ratio holes (deep holes with small diameter). The bubble blocks the plating solution from contacting the hole wall, resulting in a localized area with no copper deposition.

Improvement: Improve the activity and wetting ability of the plating chemistry, and enhance the agitation / shaking / rack oscillation effect during plating. Proper solution agitation, air sparging, and periodic rack movement help dislodge trapped bubbles. For high-aspect-ratio holes, consider reverse pulse plating or specialized high-throwing-power electrolytes.

2.3 Solder Mask / Ink in the Hole with No Protective Layer

If circuit ink (solder mask or dry film) enters the hole during pattern transfer and no proper protective layer (tin plating or dry film) is applied to the hole, the subsequent etching process will remove the copper inside the hole, resulting in a copper-free hole.

Improvement: ｒｅｐｌａｃｅ or inspect the printing screen / stencil and the counter film (artwork) to ensure proper alignment and coverage. Verify that the dry film fully covers and protects the hole walls during etching, and that solder mask application does not plug through-holes unintentionally.

2.4 Incomplete Cleaning of Acid/Alkaline Solution in Holes

After electroless copper plating or after panel electroplating, residual acid or alkaline solution inside the holes may not be fully rinsed away. These residues can contaminate subsequent process steps, cause corrosion of the deposited copper, or prevent proper adhesion of the next plating layer — ultimately leading to copper separation or voids.

Improvement: Extend the rinsing / washing time and ensure adequate water flow and pressure through the holes. Specify a maximum time window (e.g., within a defined number of hours) to complete pattern transfer after plating, to prevent oxidation or contamination of the fresh copper surface. Implement DI water quality monitoring and cascade rinsing.

2.5 Improper Operation — Excessive Micro-Etching Time

Micro-etching is a controlled process that slightly removes the copper surface to create a clean, rough surface for subsequent plating or soldermask adhesion. If the operator allows the board to remain in the micro-etch solution for too long, the thin electroless copper layer inside the holes can be completely etched away, resulting in no copper in the hole.

Improvement: Install timers and process control systems for all chemical baths. Standardize operating procedures with defined immersion times, solution temperatures, and concentration ranges. Train operators on the criticality of timing and implement first-article and in-process inspections.

2.6 Excessive Punching / Depaneling Pressure Near Conductive Holes

If the design places punching holes (tooling holes, breakaway tabs, or V-score lines) too close to conductive through-holes, the mechanical stress from punching or depaneling can crack or delaminate the copper in the nearby plated holes. Excessive punch pressure can also deform the board and damage hole wall copper.

Improvement: Add stress-relief holes in the panel design and reduce the mechanical force applied during punching or depaneling. Ensure that conductive holes are kept a safe distance from panel edges, V-score lines, and punch locations — typically at least 0.5mm, preferably 1.0mm or more.

2.7 Poor Permeability of Electroplating Solutions (Tin, Nickel)

During pattern plating, if the tin, nickel, or other plating solution has poor throwing power / permeability (ability to plate deep inside small holes), the hole walls may receive insufficient or no plating. This is especially common in high-aspect-ratio holes or when solution chemistry, temperature, or current density are not optimized.

Improvement: Conduct regular permeability / throwing-power tests (e.g., using a Haring cell or standardized test coupons) to monitor plating solution performance. Maintain solution chemistry within specification, optimize current density and agitation, and use pulse plating or high-throwing-power additives for difficult hole geometries.

3. Quality Control and Inspection Methods

To ensure hole copper quality, PCB manufacturers should implement the following inspection and control measures:

Backlight Test: A standard method to verify electroless copper coverage in through-holes. The hole is cross-sectioned or viewed under backlit illumination; any light passing through indicates incomplete copper coverage. A rating of 9.5+ (on a 10-point scale) is typically required.

Cross-Section Analysis: Physically cross-sections the hole to measure copper thickness, verify coverage, and inspect for voids, cracks, or delamination. Required per IPC-6012 for process validation.

Thermal Stress Testing: Solder float or reflow simulation followed by cross-section to verify that hole copper withstands thermal cycling without cracking.

Electrical Testing: Continuity and isolation testing to detect open circuits caused by copper-free holes.

Process Monitoring: Regular analysis of plating solution composition, pH, temperature, and additive levels; daily backlight test coupons; and statistical process control (SPC) for critical parameters.

4. Industry Standards for Hole Copper Thickness

The IPC-6012 standard defines minimum hole copper thickness requirements based on product class:

Class 1 (General Electronic Products): Minimum 15μm average, 12μm minimum at any point

Class 2 (Dedicated Service Electronic Products): Minimum 20μm average, 18μm minimum at any point

Class 3 (High Reliability Electronic Products): Minimum 25μm average, 20μm minimum at any point

Meeting these standards requires tight control of every step from drilling through final plating — and preventing the seven defect causes described above is essential.

5. Conclusion

Copper-free or insufficiently copper-plated holes are among the most common and costly defects in multilayer PCB manufacturing. The seven primary causes — drilling dust, trapped air bubbles, ink contamination, incomplete rinsing, excessive micro-etching, mechanical punch stress, and poor plating permeability — can all be effectively addressed through targeted process improvements, proper equipment maintenance, and rigorous quality control.

By implementing the corresponding solutions — high-pressure washing for small holes, improved solution agitation, proper film alignment, extended rinsing, timed chemical processes, stress-relief holes, and regular permeability testing — PCB manufacturers can significantly reduce hole copper defects, improve yield, and ensure that every plated through-hole meets IPC standards for reliability and performance.

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