High-Speed PCB Impedance Matching | Characteristic Impedance, Termination Methods & Signal Integrity

High-Speed PCB Impedance Matching | Characteristic Impedance, Termination Methods & Signal Integrity

Impedance matching is one of the most fundamental concepts in high-speed PCB design. When energy is transmitted along a transmission line, the load impedance must be equal to the characteristic impedance of the transmission line. Under this matched condition, the signal transmission produces no reflection — meaning all the energy is absorbed by the load. Conversely, when impedance is mismatched, signal reflections occur, causing energy loss, signal distortion, overshoot, undershoot, ringing, and potential circuit malfunction.

In high-speed PCB design, whether the impedance is properly matched directly determines the quality of the signal. This guide explains the principles of impedance matching, when it is required, how characteristic impedance is defined and calculated, and the most common termination methods used in modern high-speed digital design.

1. When Do PCB Traces Need Impedance Matching?

The need for impedance matching is not primarily determined by the signal frequency — the key factor is the steepness of the signal edge, i.e., the rise/fall time of the signal. A widely accepted rule of thumb is: if the signal rise/fall time (measured from 10% to 90%) is less than 6 times the trace delay, it is treated as a high-speed signal, and impedance matching must be carefully considered.

The propagation delay of a typical PCB trace on FR-4 material is approximately 150 ps per inch (about 6 ps per mm, or 150 ps/inch for outer layers and ~170 ps/inch for inner layers). For example, if a signal has a rise time of 1 nanosecond (1000 ps), the critical trace length beyond which impedance matching becomes necessary is approximately 1000 ps / (6 × 150 ps/inch) ≈ 1.1 inches. Traces longer than this should be treated as transmission lines and properly terminated.

As a practical guideline, any trace longer than one-third of the signal's effective wavelength (or the critical length calculated above) should be considered a transmission line and designed with controlled impedance and proper termination.

2. Characteristic Impedance

During signal propagation along a transmission line, if the signal propagation speed is uniform throughout the line and the capacitance per unit length is constant, the signal always sees a completely uniform instantaneous impedance during propagation. Since the impedance of the entire transmission line remains constant, this property is given a specific name — the characteristic impedance (Z₀) of the transmission line.

Characteristic impedance is defined as the value of the instantaneous impedance seen by the signal as it propagates along the transmission line. It is determined by:

The layer where the trace is located (outer layer microstrip vs. inner layer stripline)

The PCB material (dielectric constant, Dk/Er, of the substrate — typically ~4.2–4.5 for FR-4)

The trace width (wider trace = lower impedance)

The distance between the trace and the reference plane (greater distance = higher impedance)

The trace thickness (copper weight — 1oz, 2oz, etc.)

Characteristic impedance is independent of the trace length. A 1-inch 50Ω trace and a 10-inch 50Ω trace both have the same characteristic impedance.

2.1 Calculating Characteristic Impedance

Characteristic impedance can be calculated using specialized impedance calculation software, such as Polar Instruments Si8000/Si9000, Keysight ADS, Altium Designer's built-in impedance calculator, or online impedance calculators. These tools use empirical formulas (e.g., the IPC-2141 microstrip and stripline equations) or 2D field solvers to compute impedance based on the layer stackup.

2.2 Common Impedance Values

In high-speed PCB routing, digital signal traces are generally designed for 50 ohms single-ended impedance — an industry-standard approximate figure. Other common impedance values include:

Coaxial cable: 50Ω for baseband / RF, 75Ω for video / broadband (CATV)

Twisted pair (differential): 100Ω for Ethernet, 120Ω for CAN bus

USB 2.0: 90Ω differential impedance

HDMI / TMDS: 100Ω differential impedance

PCIe / SATA / DisplayPort: 85Ω or 100Ω differential impedance

DDR memory: 50Ω single-ended (point-to-point) or 40Ω for fly-by topology

PCB manufacturers typically maintain an impedance tolerance of ±10% (or ±5–7% for high-end designs) through controlled impedance manufacturing, including test coupons on the production panel for verification.

3. Common Impedance Matching (Termination) Methods

There are several termination methods used in high-speed PCB design, each with different advantages, disadvantages, and application scenarios.

3.1 Series Termination (Source-Side Series Resistor)

Under the condition that the signal source impedance is lower than the characteristic impedance of the transmission line, a resistor R is connected in series between the signal source (driver output) and the transmission line. This matches the source output impedance to the characteristic impedance of the transmission line and suppresses the re-reflection of signals reflected back from the load.

Matching resistor selection principle: The sum of the matching resistance value and the driver's output impedance equals the characteristic impedance of the transmission line. For example, if a CMOS driver has an output impedance of approximately 10–20Ω and the trace is 50Ω, a series termination resistor of 30–40Ω would be appropriate.

The output impedance of common CMOS and TTL drivers varies with the signal level (different for high and low states). Therefore, for TTL or CMOS circuits, a perfectly correct matching resistor is not possible — only a compromise value can be selected.

Important topology limitation: Signal networks with a daisy-chain (multi-drop) topology are not suitable for series termination. All loads must be connected at the end of the transmission line (point-to-point topology) for series termination to work effectively.

Advantages of series termination:

Low power consumption (no DC load on the driver)

Does not introduce additional impedance between the signal and ground

Requires only one resistive element per signal

Reduces driver-side ringing and overshoot

Common applications: General CMOS and TTL circuit impedance matching. USB signals also use this method for impedance matching (though USB 2.0 uses 45Ω series resistors on D+ and D- to achieve 90Ω differential).

3.2 Parallel Termination (Load-Side Parallel Resistor)

When the signal source impedance is very low, the input impedance at the load end is matched to the characteristic impedance of the transmission line by adding a parallel resistor, achieving the goal of eliminating reflection at the load end. This method is implemented in two forms: single-resistor and dual-resistor.

Matching resistor selection principle:

Single-resistor form: When the chip input impedance is high, the parallel resistance at the load end must be close to or equal to the characteristic impedance of the transmission line (e.g., 50Ω to ground or to VTT).

Dual-resistor (Thevenin) form: Each parallel resistor value is twice the characteristic impedance of the transmission line (e.g., two 100Ω resistors — one to VCC, one to GND — for a 50Ω line). The equivalent parallel impedance is 50Ω.

Advantages of parallel termination:

Simple and easy to implement

Effective at eliminating load-end reflections

Suitable for high-speed signals and multi-drop topologies

Disadvantages:

Introduces DC power consumption. For the single-resistor-to-ground form, DC power consumption is closely related to the signal duty cycle. For the dual-resistor (Thevenin) form, there is DC power consumption regardless of whether the signal is high or low, but the current is half that of the single-resistor method.

The single-resistor-to-VTT form requires a separate VTT power supply (termination voltage).

Common applications:

SSTL drivers such as DDR and DDR2: A single resistor is used, connected in parallel to VTT (typically half of IOVDD, e.g., 0.75V for DDR2 with 1.8V I/O). For DDR2, the parallel matching resistors for data signals are often built into the chip (on-die termination, ODT).

High-speed serial data interfaces such as TMDS (HDMI/DVI): Uses a single-resistor form, connected in parallel to IOVDD at the receiving device end, with single-ended impedance of 50Ω (100Ω between differential pairs).

LVDS (Low-Voltage Differential Signaling): Typically uses a 100Ω differential termination resistor across the pair at the receiver.

3.3 Additional Termination Methods

Beyond series and parallel termination, several other methods are used in specific applications:

Thevenin termination (dual-resistor): As described above, uses two resistors (one to VCC, one to GND) at the load. Provides both impedance matching and DC bias, but consumes constant DC power. Suitable for TTL/CMOS signals.

RC termination (parallel resistor + capacitor to ground): A resistor in series with a capacitor connected to ground at the load. The resistor provides impedance matching, while the capacitor blocks DC current, eliminating DC power consumption. Suitable for signals with 50% duty cycle (e.g., clocks). The RC time constant must be much larger than the signal period.

Diode clamping termination: Uses Schottky diodes to clamp overshoot and undershoot to the power rails. Does not provide true impedance matching but limits ringing amplitude. Often used in combination with other termination methods for voltage-sensitive inputs.

On-Die Termination (ODT): Modern high-speed memory (DDR3/DDR4/DDR5) and some FPGAs integrate termination resistors inside the chip, eliminating the need for external components and improving signal integrity at high data rates.

4. Practical Design Considerations

When implementing impedance matching in a high-speed PCB design, keep the following practical considerations in mind:

4.1 Termination Resistor Placement

For series termination, place the resistor as close as possible to the driver output pin (within 0.5 inch / 12mm) to minimize the stub between the driver and the resistor.

For parallel termination, place the resistor as close as possible to the receiver input pin to minimize the stub at the load end.

For differential pairs, place the differential termination resistor directly across the pair at the receiver, with minimal stub length.

4.2 Reference Plane Continuity

Impedance control depends on a continuous, solid reference plane (ground or power) directly beneath the trace. Any gap, split, or cutout in the reference plane under a controlled-impedance trace will cause an impedance discontinuity, signal reflection, and increased EMI. Always verify that high-speed traces have an uninterrupted return path.

4.3 Via Impact on Impedance

Vias introduce impedance discontinuities (typically 1–4nH inductance and 0.3–0.8pF capacitance). For high-speed signals, minimize the number of vias, use back-drilling to remove via stubs, and consider via impedance compensation (anti-pad sizing) for very high-speed serial links (10Gbps+).

4.4 Impedance Verification

After PCB fabrication, verify impedance using test coupons included on the production panel. Time Domain Reflectometry (TDR) is the standard method for measuring characteristic impedance and identifying impedance discontinuities along the trace.

5. Conclusion

Impedance matching is essential for ensuring signal integrity in high-speed PCB design. The need for matching is determined by the signal's rise/fall time relative to trace delay, not simply by clock frequency. Characteristic impedance — determined by trace width, dielectric constant, layer configuration, and distance to the reference plane — must be carefully calculated and controlled during both design and manufacturing.

Series termination is the most common method for point-to-point CMOS/TTL signals, offering low power consumption and simplicity. Parallel termination (including VTT-based SSTL for DDR memory and differential termination for high-speed serial interfaces) is preferred for high-speed and multi-drop applications. Additional methods such as Thevenin, RC, diode clamping, and on-die termination provide options for specific design requirements.

By understanding these principles and applying the appropriate termination strategy — along with proper resistor placement, continuous reference planes, and impedance verification — designers can ensure reliable, high-quality signal transmission in even the most demanding high-speed PCB designs.

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