PCB Via Design Guide: 6 Common Via Treatment Methods & Best Practices for High-Density Boards

PCB Via Design Guide: 6 Common Via Treatment Methods & Best Practices for High-Density Boards

Vias are one of the most critical components of multilayer PCBs, with drilling costs typically accounting for 30% to 40% of total PCB manufacturing expenses. Structurally, a via consists of two parts: the central drill hole, and the surrounding annular pad ring.

In high-speed, high-density PCB design, designers generally prefer smaller vias to free up more routing space and reduce parasitic capacitance for better high-speed signal performance. However, via size cannot be reduced indefinitely, as it is limited by drilling and plating process capabilities: smaller holes require longer drilling time and have higher risk of drill offset; when the via depth exceeds 6 times the hole diameter (6:1 aspect ratio), uniform copper plating on hole walls can no longer be guaranteed.

Balancing design performance, manufacturing feasibility and production cost is the core of via design. Below are 6 standard via treatment rules and best practices for conventional PCB design.

1. Standard Through-Hole Via Size Specification

For standard through-hole vias:

Minimum inner drill diameter is 0.2mm (8mil) in principle, with minimum outer pad diameter of 0.4mm (16mil). For space-constrained areas, outer pad can be reduced to 0.35mm (14mil) as a special case.

A general industry rule of thumb for via size: outer pad diameter ≈ inner diameter × 2 ± 2mil. For example, an 8mil inner diameter via can be designed as 8/14mil, 8/16mil or 8/18mil; a 12mil inner diameter via can be 12/22mil, 12/24mil or 12/26mil.

2. Blind & Buried Via Design Rules

Blind and buried vias are mainly used for high-density HDI boards, but significantly increase production cost.

For BGA designs with pitch of 0.65mm and above, blind/buried vias are generally not recommended due to the substantial cost increase.

When blind vias are required, first-order blind vias (TOP to Layer 2, or BOTTOM to Layer -2) are the most cost-effective option. Standard first-order blind via size is 0.1mm (4mil) inner diameter with 0.25mm (10mil) outer pad.

3. Via to Component Pad Clearance

Vias must not be placed directly on pads for 0402 and smaller passive components (resistors and capacitors). While placing vias on pads theoretically adds minimal series inductance, during SMT assembly solder paste will flow into the via, causing uneven solder volume and tombstoning (component standing up) defects.

Recommended clearance between via edge and small component pad edge: 4–8mil.

4. Via-to-Via Spacing Requirements

Insufficient spacing between adjacent vias increases the risk of drill breakout, hole wall damage and board delamination.

Recommended minimum via center-to-center spacing: 0.5mm and above for standard designs

Spacing of 0.35–0.4mm should be avoided where possible

Spacing of 0.3mm and below is prohibited for mass production

5. Via Plugging & Solder Mask Tenting Best Practices

For through-holes with diameter ≤0.5mm (and all vias with inner diameter ≤0.4mm), solder mask tenting or full via plugging is required for most applications.

Key Application Rules

Under metal-case components: Never place vias directly under the device body. If vias are unavoidable near the package, they must be fully plugged and covered with solder mask to prevent short circuits between the metal case and exposed via copper.

Under BGA arrays: Vias placed between BGA pads must be centered between two adjacent pads to maintain equal distance to both pads. Uneven via placement can cause assembly process issues and soldering quality risks. All vias under BGA must be fully plugged with solder mask to prevent solder ball short circuits during reflow.

6. Reinforcement Vias for Mechanical Pads

For fixed mechanical pads of components such as headphone jacks, buttons and FPC connectors, 1–2 evenly spaced vias can be added to the pad when space allows. These vias anchor the pad to inner copper layers, effectively improving pad adhesion strength and preventing pad peeling under mechanical stress.

Conclusion

Via design is a core trade-off between routing density, high-speed performance and manufacturing cost. Following standard size specifications, spacing rules and plugging requirements ensures vias meet both electrical performance and mass production yield requirements, avoiding unnecessary cost increases and assembly defects.

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